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158
W158
Spread Spectrum System Frequency Synthesizer
Features
* Maximized EMI suppression using Cypress's spread spectrum technology * Intel(R) CK98 Specification compliant * 0.5% downspread outputs deliver up to 10 dB lower EMI * Four skew-controlled copies of CPU output * Eight copies of PCI output (synchronous w/CPU output) * Four copies of 66 MHz fixed frequency 3.3V clock * Two copies of CPU/2 outputs for synchronous memory reference * Three copies of 16.67 MHz IOAPIC clock, synchronous to CPU clock * One copy of 48 MHz USB output * Two copies of 14.31818 MHz reference clock * Programmable to 133- or 100-MHz operation * Power management control pins for clock stop and shut down * Available in 56-pin SSOP ............................................................................................... VDDQ2 = 2.5V5% CPU Output Jitter: ...................................................... 150 ps CPUdiv2, IOAPIC Output Jitter: .................................. 250 ps 48 MHz, 3V66, PCI Output Jitter: ................................ 500 ps CPU0:3, CPUdiv2_ 0:1 Output Skew: ......................... 175 ps PCI_F, PCI1:7 Output Skew: ....................................... 500 ps 3V66_0:3, IOAPIC0:2 Output Skew: ........................... 250 ps CPU to 3V66 Output Offset: ........... 0.0 to1.5 ns (CPU leads) 3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads) CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads) CPU to PCI Output Offset:............. 1.5 to 4.0 ns (CPU leads) Logic inputs, except SEL133/100#, have 250-k resistors Table 1. Pin Selectable Frequency[1] SEL133/100# 1 0 CPU0:3 (MHz) 133 MHz 100 MHz PCI 33.3 MHz 33.3 MHz pull-up
Key Specifications
Supply Voltages: ...................................... VDDQ3 = 3.3V5%
Note: 1. See Table 2 for complete mode selection details.
Block Diagram
X1 X2 CPU_STOP#
Pin Configuration
2 REF0:1
XTAL OSC
STOP Clock Logic
4 CPU0:3
2 SPREAD# SEL0 SEL1 SEL133/100# /2//1.5 /2 CPUdiv2_0:1
PLL 1
STOP Clock Logic 4 3V66_0:3
1 PCI_F STOP Clock Logic 7 PCI1:7
PWRDWN# PCI_STOP#
/2
Power Down Logic
3 /2 IOAPIC0:2
GND REF0 REF1 VDDQ3 X1 X2 GND PCI_F PCI1 VDDQ3 PCI2 PCI3 GND PCI4 PCI5 VDDQ3 PCI6 PCI7 GND GND 3V66_0 3V66_1 VDDQ3 GND 3V66_2 3V66_3 VDDQ3 SEL133/100#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDDQ2 IOAPIC2 IOAPIC1 IOAPIC0 GND VDDQ2 CPUdiv2_1 CPUdiv2_0 GND VDDQ2 CPU3 CPU2 GND VDDQ2 CPU1 CPU0 GND VDDQ3 GND PCI_STOP# CPU_STOP# PWRDWN# SPREAD# SEL1 SEL0 VDDQ3 48MHz GND
W158
Three-state Logic
PLL2
1
48MHz
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 12
www.SpectraLinear.com
W158
Pin Definitions
Pin Pin No. Type Pin Description 41, 42, 45, 46 O CPU Clock Outputs 0 through 3: These four CPU clocks run at a frequency set by SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2. CPUdiv2_ 0:1 49, 50 O Synchronous Memory Reference Clock Output 0 through 1: Reference clock for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage swing is set by the voltage applied to VDDQ2. PCI1:7 9, 11, 12, 14, O PCI Clock Outputs 1 through 7: These seven PCI clock outputs run synchronously to 15, 17, 18 the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI1:7 outputs are stopped when PCI _STOP# is held LOW. PCI_F 8 O PCI_F (PCI Free-running): This PCI clock output runs synchronously to the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI_F is not affected by the state of PCI_STOP#. REF0:1 2, 3 O 14.318-MHz Reference Clock Output: 3.3V copies of the 14.318-MHz reference clock. IOAPIC0:2 53, 54, 55 O I/O APIC Clock Output: Provides 16.67-MHz fixed frequency. The output voltage swing is set by the power connection to VDDQ2. 48MHz 30 O 48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage applied to VDDQ3. 3V66_0:3 21, 22, 25, 26 O 66-MHz Output 0 through 3: Fixed 66-MHz outputs. Output voltage swing is controlled by voltage applied to VDDQ3. SEL0:1 32, 33 I Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output modes. SEL133/100# 28 I Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output frequency as shown in Table 1. X1 5 I Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or an external reference signal. X2 6 O Crystal Connection: An output connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. SPREAD# 34 I Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables spread spectrum mode when held LOW. PWRDWN# 35 I Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that requests the device to enter power-down mode. CPU_STOP# 36 I Active LOW CPU Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all CPU and 3V66 clocks when held LOW. CPUdiv2 outputs are unaffected by this input. PCI_STOP# 37 I Active LOW PCI Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all PCI outputs except PCI_F when held LOW. VDDQ3 4, 10, 16, 23, P Power Connection: Power supply for PCI output buffers, 48-MHz USB output buffer, 27, 31, 39 Reference output buffers, 3V66 output buffers, core logic, and PLL circuitry. Connect to 3.3V supply. VDDQ2 43, 47, 51, 56 P Power Connection: Power supply for IOAPIC, CPU, and CPUdiv2 output buffers. Connect to 2.5V supply. G Ground Connection: Connect all ground pins to the common system ground plane. GND 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 Pin Name CPU0:3
Overview
The W158 is designed to provide the essential frequency sources to work with advanced multiprocessing Intel architecture platforms. Split voltage supply signaling provides 2.5V and 3.3V clock frequencies operating up to 133 MHz. From a low-cost 14.31818-MHz reference crystal oscillator, the W158 generates 2.5V clock outputs to support CPUs, core logic chip set, and Direct RDRAM clock generators. It also provides skew-controlled PCI and IOAPIC clocks synchronous to CPU clock, 48-MHz Universal Serial Bus
(USB) clock, and replicates the 14.31818-MHz reference clock. All CPU, PCI, and IOAPIC clocks can be synchronously modulated for spread spectrum operations. Cypress employs proprietary techniques that provide the maximum EMI reduction while minimizing the clock skews that could reduce system timing margins. Spread Spectrum modulation is enabled by the active LOW control signal SPREAD#. The W158 also includes power management control inputs. By using these inputs, system logic can stop CPU and/or PCI clocks or power down the entire device to conserve system power. Page 2 of 12
Rev 1.0, November 21, 2006
W158
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is -0.5% downspread. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices.
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100%
Frequency Shift
10%
20%
30%
40%
50%
60%
70%
80%
90%
10%
20%
30%
40%
50%
60%
70%
80%
100%
90%
Time
Figure 2. Modulation Waveform Profile
Rev 1.0, November 21, 2006
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100%
W158
Mode Selection Functions
The W158 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs. Table 2. Select Functions SEL133/100# 0 0 0 0 1 1 1 1 Table 3. Truth Table SEL 133/100# 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 CPU HI-Z n/a 100 MHz 100 MHz TCLK/2 n/a 133 MHz 133 MHz CPUdiv2 HI-Z n/a 50 MHz 50 MHz TCLK/4 n/a 66 MHz 66 MHz 3V66 HI-Z n/a 66 MHz 66 MHz TCLK/4 n/a 66 MHz 66 MHz PCI HI-Z n/a 33 MHz 33 MHz TCLK/8 n/a 33 MHz 33 MHz 48MHz HI-Z n/a HI-Z 48 MHz TCLK/2 n/a HI-Z 48 MHz REF HI-Z n/a IOAPIC HI-Z n/a 3 4, 7, 8 5, 6 3 4, 7, 8 Notes 2 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 (Reserved) Active 100-MHz, 48-MHz PLL Inactive Active 100-MHz, 48-MHz PLL Active Test Mode (Reserved) Active 133-MHz, 48-MHz PLL Inactive Active 133-MHz, 48-MHz PLL Active Function All Outputs Three-State
14.318 MHz 16.67 MHz 14.318 MHz 16.67 MHz TCLK n/a TCLK16 n/a
14.318 MHz 16.67 MHz 14.318 MHz 16.67 MHz
Table 4. Maximum Supply Current Max. 2.5V supply consumption Max. discrete cap loads, VDDQ2=2.625V All static inputs=VDDQ3 or GND 100 A 75 mA Max. 3.3V supply consumption Max. discrete cap loads, VDDQ3=3.465V or GND 200 A 160 mA
Condition Powerdown Mode (PWRDWN#=0) Full Active 100 MHz SEL133/100#=0 SEL1, 0=11 CPU_STOP#, PCI_STOP#=1 Full Active 133 MHz SEL133/100#=0 SEL1, 0=11 CPU_STOP#, PCI_STOP#=1
90 mA
160 mA
Notes: 2. Provided for board level "bed of nails" testing. 3. 48-MHz PLL disabled to reduce component jitter. 4. Normal" mode of operation. 5. TCLK is a test clock over driven on the X1 input during test mode. TCLK mode is based on 133-MHz CPU select logic. 6. Required for DC output impedance verification. 7. Range of reference frequency is min.=14.316, nominal = 14.31818 MHz, max.=14.32 MHz. 8. Frequency accuracy of 48 MHz is +167 PPM to match USB default.
Rev 1.0, November 21, 2006
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W158
Table 5. Clock Enable Configuration[9, 10, 11, 12, 13, 14] CPU_STOP# PWRDWN# PCI_STOP# X 0 0 1 1 0 1 1 1 1 X 0 1 0 1 CPU LOW LOW LOW ON ON CPUdiv2 IOAPIC LOW ON ON ON ON LOW ON ON ON ON 3V66 LOW LOW LOW ON ON PCI LOW LOW ON LOW ON PCI_F LOW ON ON ON ON REF, 48MHz LOW ON ON ON ON OSC. OFF ON ON ON ON VCOs OFF ON ON ON ON
Table 6. Power Management State Transition[15, 16] Latency Signal CPU_STOP# PCI_STOP# PWRDWN# Signal State 0 (disabled) 1 (enabled) 0 (disabled) 1 (enabled) 1 (normal operation) 0 (power down) No. of rising edges of PCI Clock 1 1 1 1 3 ms 2 max.
Timing Diagrams
CPU_STOP# Timing Diagram[17, 18, 19, 20, 21, 22]
CPU
(internal)
PCI CPU_STOP# PCI_STOP# PWRDWN#
HI HI
CPU
(external)
3V66
Notes: 9. LOW means outputs held static LOW as per latency requirement below. 10. ON means active. 11. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs. 12. All 3V66 as well as all CPU clocks stop cleanly when CPU_STOP# is pulled LOW. 13. CPUdiv2, IOAPIC, REF, 48MHz signals are not controlled by the CPU_STOP# functionality and are enabled in all conditions except PWRDWN#=LOW. 14. An "x" indicates a "don't care" condition. 15. Clock on/off latency is defined in the number of rising edges of the free-running PCI clock between when the clock disable goes LOW/HIGH to when the first valid clock comes out of the device. 16. Power up latency is from when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device. 17. All internal timing is referenced to the CPU clock. 18. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed. 19. CPU_STOP# signal is an input signal that must be made synchronous to free-running PCI_F. 20. 3V66 clocks also stop/start before. 21. PWRDWN# and PCI_STOP# are shown in a HIGH state. 22. Diagrams shown with respect to 133 MHz. Similar operation when CPU clock is 100 MHz.
Rev 1.0, November 21, 2006
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W158
Timing Diagrams (continued)
PCI_STOP# Timing Diagram[18, 22, 23, 24, 25, 26]
CPU
PCI
(internal)
PCI_STOP# CPU_STOP# PWRDWN# PCI_F
(external)
HI HI
PCI
(external)
PWRDWN# Timing Diagram[18, 22, 23, 27, 28]
CPU (internal) PCI (internal) PWRDWN# CPU (external) PCI (external) VCO
Crystal Notes: 23. All internal timing is referenced to the CPU clock. 24. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output. 25. All other clocks continue to run undisturbed. 26. PWRDWN# and CPU_STOP# are shown in a HIGH state. 27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal must be synchronized. 28. The shaded Sections on the VCO and the Crystal signals indicate an active clock.
Rev 1.0, November 21, 2006
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W158
Absolute Maximum Ratings[29]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi.
tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TA TB ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDD-3.3V IDD-2.5 VIL VIH IIL IIH IIL IIH Combined 3.3V Supply Current Combined 2.5V Supply Current Input Low Voltage Input High Voltage Input Low Current[31] Input High Current[31] SEL133/100#[31] SEL133/100#[31] Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.25V VOH = 1.25V Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V 3.1 70 65 100 95 145 135 3.1 45 45 Min. 65 65 Typ. 100 100 Max. 50 2.2 45 45 Min. 65 65 Typ. 100 100 Max. 50 Min. Typ. Input Low Current, Input High Current, CPU0:3 =133 MHz[30] CPU0:3 =133 MHz[30] GND -0.3 2.0 160 90 0.8 VDD+ 0.3 -25 10 -5 5 Max. 50 mA mA V V A A A A Unit mV V mA mA Unit mV V mA mA Unit mV V mA mA Description Test Condition Min. Typ. Max. Unit
Logic Inputs (All referenced to VDDQ3 = 3.3V)
Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2) VOL VOH IOL IOH VOL VOH IOL IOH VOL VOH IOL IOH Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Voltage Output High Voltage Output Low Current Output High Current
48MHz, REF (Referenced to VDDQ3)
PCI, 3V66 (Referenced to VDDQ3)
Notes: 29. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 30. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 31. W158 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
Rev 1.0, November 21, 2006
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W158
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input threshold Voltage[32] Load Capacitance, Imposed on External Crystal[33] X1 Input Capacitance[34] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 1.65 18 28 5 6 7 V pF pF pF pF nH Description Test Condition Min. Typ. Max. Unit
Pin Capacitance/Inductance
3.3V AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V 5%, fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[35] 3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF) Parameter f tR tF tD fST Description Frequency Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Note 36 Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 1 45 Min. Typ. 66.6 4 4 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
Notes: 32. X1 input threshold voltage (typical) is VDD/2. 33. The W158 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 34. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 35. Period, jitter, offset, and skew measured on rising edge at 1.5V. 36. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
Rev 1.0, November 21, 2006
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W158
PCI Clock Outputs, PCI_F and PCI1:7 (Lump Capacitance Test Load = 30 pF) Parameter tP tH tL tR tF tD tJC tSK tO tq fST Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew 3V66 to PCI Clock Skew Test Condition/Comments Measured on rising edge at 1.5V[37] Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all 3V66/PCI outputs. Measured on rising edge at 1.5V. 3V66 leads PCI output. 1.5 1.5 Min. 30 12 12 1 1 45 4 4 55 500 500 3 4 3 Typ. Max. Unit ns ns ns V/ns V/ns % ps ps ns ns ms
Output Rise Edge Rate Measured from 0.4V to 2.4V
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Frequency Stabilization from Power-up (cold start) AC Output Impedance Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value.
Zo
15
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
Note: 37. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
Rev 1.0, November 21, 2006
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W158
2.5V AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2= 2.5V5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[38] CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 7.5 1.87 1.67 1 1 45 4 4 55 150 7.65 CPU = 100 MHz Typ. Max. Unit 10.2 ns ns ns 4 4 55 150 V/ns V/ns % ps 10 3.0 2.8 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 15 5.25 5.05 1 1 45 4 4 55 250 15.3 CPU = 100 MHz Typ. Max. Unit 20.4 ns ns ns 4 4 55 250 V/ns V/ns % ps 20 7.5 7.3 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
Note: 38. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
Rev 1.0, November 21, 2006
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W158
IOAPIC Clock Outputs, IOAPIC0:2 (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Note 39 Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 1 1 45 Test Condition/Comments Min Typ 16.67 4 4 55 3 Max Unit MHz V/ns V/ns % ms
Zo
Note: 39. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Rev 1.0, November 21, 2006
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W158
Ordering Information
Ordering Code W158 Package Name H Package Type 56-pin SSOP (300 mils)
Package Diagram
56-lead Shrunk Small Outline Package O56
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 21, 2006
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